1. Field of the Invention
The invention relates to the field of microelectronics and in particular to the fabrication of microcircuits on porous substrates with high resolution and the structures fabricated thereby.
2. Description of the Prior Art
Interest in porous materials has mainly been because of its altered material properties in comparison to compact matter. Examples are nano- or aerogel thermal insulators or in micro devices using porous silicon membranes. Porosity may also lead to lowered dielectric constants of matter or changes in electrical resistivity. If the pores are well ordered like in anodized alumina, they could be additionally used in functional structures where the pores serve as line connections between various levels of a three dimensional structure.
Micromachining bears some problems in the case of large scale precision machining of porous matter, because the widely used technique of resist lithography does not work on porous materials. The resist is sucked into the inner pores where dissolution is later hindered or difficult to achieve. Alternative strategies which have been used to surmount this problem are methods which deposit the porous material through a hard mask, such as in metal-oxide gas sensors, or which depose the porous material on top of an already patterned resist prepared for lift off.
For those layers, which have to be made porous after depositing a bulk material, this starting layer may be structured before processing. Etching the starting material or partially covering it with an anodizing-resistant layer may do this. However, these techniques do not provide parallel pores at the edges of the porous layer, as the processes are isotropic. As a rule of thumb the width of edge disordering will be equal to the starting material thickness.
Therefore, if ordering of pores will be essentially required, the present state of the art of structuring in porous material leads to large minimum feature sizes since the isotropic porous edge region cannot be used. A new method of patterning porous material is needed which maintains pore ordering and which makes feature sizes down to the inter-pore distance possible. From this, new applications of porous layers will arise.
The invention is a method of fabricating electrically passive components or optical elements on top or underneath of an integrated circuit by using a porous substrate that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. The invention is directed to a method of fabricating electrically passive components like inductors, capacitors, interconnects and resistors or optical elements like light emitters, waveguides, optical switches of filters on top or underneath of an integrated circuit by using porous material layer that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. In the illustrated embodiment the fabrication of voluminous, solenoid-type inductive elements in a porous insulating material by standard back- and front-side-lithography and contacting these two layers by electroplating micro-vias through the pores is described. By using a very dense interconnect spacing, an inter-pore capacitor structure is obtained between the metalized pores and the pore walls utilized as insulators.
The invention is a method of fabricating an intermediate structure in a porous substrate in which microdevices are fabricated and which porous substrate has a frontside with a plurality of open pores and an opposing backside wherein the plurality of pores are closed. The method comprises the steps of disposing a patterned photolithographed mask on the backside. Selected portions of the backside are removed to leave a portion of the porous substrate intact to define open pore portions and to leave a portion of the porous substrate with the backside removed to define a plurality of disconnected segments. The disconnected segments in turn define pore walls for a subplurality of doubly-opened pores which are open on each opposing end of the pore. By this means an intermediate structure is formed in which microdevices may be fabricated.
The method further comprises the step of selectively removing the plurality of disconnected segments to form a plurality of disconnected open pore substrate portions as an intermediate structure in which microdevices may be formed.
The method further comprises electroplating the backside to fill the doubly-opened pores with a filler material to define a filled pore portion and to create a starting electroplated layer on the backside.
The method further comprises further electroplating the backside to form a final electroplated layer of material thereon acting as a backing layer.
The method further comprises disposing an insulating layer on the backside prior to further electroplating the backside to form a final electroplated layer in order to reduce thickness of the final electroplated layer on the backside.
The method further comprises selectively removing open pore substrate portions to leave a filled pore portion.
The method further comprises removing the final electroplated layer on the backside to leave a free standing filled pore portion.
The method further comprises utilizing the free standing filled pore portion as an interconnect layer in a flip-chip hybrid circuit.
The method further comprises utilizing the free standing filled pore portion as a two-dimensional Zebra-connector between two surfaces bearing contact bumps which in turn are attached to connectors formed on both sides of the Zebra-connector.
The method further comprises filling in the disconnected segments with a filler material, selectively filling in the open pore portions with a conductive material and forming an array of two parallel rows of connectors through the porous substrate, and disposing metallizations on the frontside and backside of the porous substrate coupling alternate ones of the connectors in each of the two parallel rows of connectors to form a conductive coil in the porous substrate.
In one embodiment the step of filling in the disconnected segments with a filler material comprises filling in the disconnected segments with a magnetically permeable material.
The step of disposing metallizations on the frontside and backside of the porous substrate comprises disposing diagonal metallizations on the frontside and backside of the porous substrate to connect opposing connectors in the two rows.
In another embodiment the step of disposing metallizations on the frontside and backside of the porous substrate comprises disposing double metallizations which are insulated from each other so that two electrically separate coils are formed in the porous substrate.
The step of forming an array of two parallel rows of connectors through the porous substrate further comprises forming four parallel rows of connectors so that two concentric coils are formed therefrom.
The method further comprises forming a conductive contact on the frontside and backside of the porous substrate and coupling each of the conductive contacts with one end of the coil.
The method further comprises selectively removing the open pore substrate portions to leave the plurality of disconnected segments. A first conductive layer is disposed on a first end of the disconnected segments. A second conductive layer is disposed on the pore walls, on the first conductive layer exposed in the pore, and on a second end of the disconnected segments opposing the first end. An insulating layer is disposed on the second conductive layer. A third conductive layer is disposed on the insulating layer to fill the pores and to form a conductive backside layer so that a capacitor is formed.
The method further comprises electroplating a starting layer on the first end of the disconnected segments.
The step of disposing a first conductive layer on a first end of the disconnected segments comprises electroplating a conductive partial layer partially extending into the pores. disposing a seed layer within the pores and on the second end of the disconnected segments and on the conductive partial layer within the pores, and electroplating a conductive final layer on the seed layer. The conductive partial layer, seed layer and conductive final layer comprise the second conductive layer.
The step of disposing an insulating layer on the second conductive layer comprises partially converting the conductive final layer into a first insulating layer and disposing a second insulating layer thereon.
The step of disposing a third conductive layer on the insulating layer comprises disposing a second seed layer on the insulating layer and electroplating an electrode layer thereon to fill the pores and to provide the backing.
The invention is also defined as the intermediate structures and apparatus formed by the above methods. Although the methods have for the sake of grammatical ease been described in many cases as steps, it is to be expressly understood that the invention is not to be limited by the construction of means or steps based on 35 USC 112. The invention can be better visualized by turning to the following drawings wherein like elements are referenced by like numerals.